GitHub / wsipak
Total Commits: 219
chipsalliance/cores-veer-el2
Commits: 69
zephyrproject-rtos/zephyr
Primary Git Repository for the Zephyr Project. Zephyr is a new generation, scalable, optimized, secure RTOS for multiple hardware architectures.
Commits: 50
zmkfirmware/zephyr
Primary Git Repository for the Zephyr Project. Zephyr is a new generation, scalable, optimized, secure RTOS for multiple hardware architectures.
Commits: 32
nrfconnect/sdk-zephyr
Commits: 25
platformio/zephyr
Commits: 25
chipsalliance/verible-linter-action
Automatic SystemVerilog linting in github actions with the help of Verible
Commits: 24
microsoft/cheriot-ibex
cheriot-ibex is a RTL implementation of CHERIoT ISA based on LowRISC's Ibex core.
Commits: 6
chipsalliance/verible
Verible is a suite of SystemVerilog developer tools, including a parser, style-linter, formatter and language server
Commits: 6
litex-hub/pythondata-cpu-ibex
Commits: 3
lowrisc/ibex
Commits: 3
3mdeb/verible
Commits: 3
utzig/zephyr
Commits: 2
3mdeb/zephyr
Commits: 2
renode/renode-infrastructure
Commits: 2
chipsalliance/uhdm
Universal Hardware Data Model. A complete modeling of the IEEE SystemVerilog Object Model with VPI Interface, Elaborator, Serialization, Visitor and Listener. Used as a compiled interchange format in between SystemVerilog tools. Compiles on Linux gcc, Windows msys2-gcc & msvc, OsX
Commits: 2
renode/renode
Renode - Antmicro's open source simulation and virtual development framework for complex embedded systems
Commits: 2
LibreSolar/zephyr
Commits: 2
dop-amin/opentitan
Commits: 1
Willmish/cantrip
Commits: 1
ben-ph/sel4
Commits: 1
lowRISC/opentitan
Commits: 1