An open API service providing commit metadata for open source projects.

GitHub / tgorochowik

Total Commits: 5

platformio/zephyr

Commits: 98

zephyrproject-rtos/zephyr

Primary Git Repository for the Zephyr Project. Zephyr is a new generation, scalable, optimized, secure RTOS for multiple hardware architectures.

Commits: 98

zmkfirmware/zephyr

Primary Git Repository for the Zephyr Project. Zephyr is a new generation, scalable, optimized, secure RTOS for multiple hardware architectures.

Commits: 95

LibreSolar/zephyr

Commits: 95

3mdeb/zephyr

Commits: 95

utzig/zephyr

Commits: 93

aaronc81/zephyr

Zephyr with board definitions from https://github.com/najnesnaj/pinetime-zephyr

Commits: 93

chipsalliance/synlig

SystemVerilog synthesis tool

Commits: 37

chipsalliance/verible

Verible is a suite of SystemVerilog developer tools, including a parser, style-linter, formatter and language server

Commits: 25

3mdeb/verible

Commits: 24

jbampton/verible

Commits: 18

radareorg/radare2

UNIX-like reverse engineering framework and command-line toolset

Commits: 12

renode/renode

Renode - Antmicro's open source simulation and virtual development framework for complex embedded systems

Commits: 10

chipsalliance/verible-linter-action

Automatic SystemVerilog linting in github actions with the help of Verible

Commits: 9

civetweb/civetweb

Embedded C/C++ web server

Commits: 9

timkpaine/Surelog

Commits: 5

MikePopoloski/slang

Commits: 5

verilator/verilator

Commits: 5

chipsalliance/surelog

SystemVerilog 2017 Pre-processor, Parser, Elaborator, UHDM Compiler. Provides IEEE Design/TB C/C++ VPI and Python AST & UHDM APIs. Compiles on Linux gcc, Windows msys2-gcc & msvc, OsX

Commits: 5

antmicro/rdfm

Commits: 3

dop-amin/opentitan

Commits: 3

tgorochowik/fr24-tweaks

:airplane: Notification zone hack for flightradar24 :satellite:

Commits: 3

maijin/testsubtree

testsubtree

Commits: 2

home-assistant/core

:house_with_garden: Open source home automation that puts local control and privacy first.

Commits: 2

rizinorg/rizin

UNIX-like reverse engineering framework and command-line toolset.

Commits: 2

rizinorg/rizin

UNIX-like reverse engineering framework and command-line toolset.

Commits: 2

chipsalliance/uhdm

Universal Hardware Data Model. A complete modeling of the IEEE SystemVerilog Object Model with VPI Interface, Elaborator, Serialization, Visitor and Listener. Used as a compiled interchange format in between SystemVerilog tools. Compiles on Linux gcc, Windows msys2-gcc & msvc, OsX

Commits: 2

silverbulletmd/silverbullet

An open source personal productivity platform built on Markdown, turbo charged with the scripting power of Lua

Commits: 2

opencollective/radare2

unix-like reverse engineering framework and commandline tools

Commits: 2

rommapp/romm

A beautiful, powerful, self-hosted rom manager and player.

Commits: 1

rpi-distro/bluez

Commits: 1

chipsalliance/cores-veer-eh1

VeeR EH1 core

Commits: 1

zachjs/sv2v

SystemVerilog to Verilog conversion

Commits: 1

saravieira/romm

Commits: 1

janisozaur/bluez

Commits: 1

hadess/bluez

BlueZ fork with topic branches

Commits: 1

mayank1513/opencv

Commits: 1

xypron/nezha-u-boot

Commits: 1

siemens/u-boot

U-Boot

Commits: 1

manchoz/bluez

Commits: 1

xiaoyur347/bluez

Commits: 1

microsoft/opencv

Commits: 1

xiaoyur347/bluez

Commits: 1

openhwgroup/u-boot

Commits: 1

bluez/bluez

Main BlueZ tree

Commits: 1

Koenkk/zigbee-herdsman-converters

Collection of device converters to be used with zigbee-herdsman

Commits: 1

Koenkk/zigbee-herdsman-converters

Collection of device converters to be used with zigbee-herdsman

Commits: 1

opencv/opencv

Open Source Computer Vision Library

Commits: 1

chipsalliance/riscv-dv

Random instruction generator for RISC-V processor verification

Commits: 1

huningxin/opencv

Commits: 1

NVIDIA/u-boot

Commits: 1