siliconcompiler/siliconcompiler

Commits: 1,378

nmoroze/tclint

Commits: 281

nmoroze/peer-edit

Commits: 102

zeroasiccorp/switchboard

Commits: 59

CodeChefVIT/DevTris

Hexagon shaped Tetris game called Hextris in the DEVSOC 21 theme.

Commits: 56

Hextris/hextris

Fast paced HTML5 puzzle game inspired by Tetris!

Commits: 56

nmoroze/blog

Personal blog for writing about my projects

Commits: 33

lowRISC/opentitan

Commits: 21

The-OpenROAD-Project/OpenROAD

OpenROAD's unified application implementing an RTL-to-GDS Flow. Documentation at https://openroad.readthedocs.io/en/latest/

Commits: 12

aolofsson/oh

Verilog library for ASIC and FPGA designers

Commits: 10

anishathalye/rtlv

Commits: 10

zeroasiccorp/umi

Commits: 4

riscv-collab/riscv-openocd

Fork of OpenOCD that has RISC-V support

Commits: 4

openocd-org/openocd

Official OpenOCD Read-Only Mirror (no pull requests)

Commits: 4

espressif/openocd-esp32

OpenOCD branch with ESP32 JTAG support

Commits: 4

sysprogs/openocd

OpenOCD shipped with VisualGDB. Built with CMake.

Commits: 4

siliconcompiler/lambdalib

Commits: 4

raspberrypi/openocd

Commits: 4

dop-amin/opentitan

Commits: 3

nmoroze/slic3r-config

Config files for Slic3r.

Commits: 3

litex-hub/pythondata-misc-opentitan

Commits: 3

efeslab/yosys

Commits: 2

uwsampl/yosys

Commits: 2

flaviens/cellift-yosys

Commits: 2

uwsampl/gus-yosys

Commits: 2

YosysHQ/yosys

Yosys Open SYnthesis Suite

Commits: 2

chipsalliance/surelog

SystemVerilog 2017 Pre-processor, Parser, Elaborator, UHDM Compiler. Provides IEEE Design/TB C/C++ VPI and Python AST & UHDM APIs. Compiles on Linux gcc, Windows msys2-gcc & msvc, OsX

Commits: 1

nmoroze/sby-experiments

Commits: 1

timkpaine/Surelog

Commits: 1

steveicarus/iverilog

Icarus Verilog

Commits: 1

nmoroze/avh-getstarted

Commits: 1

Xilinx/libsystemctlm-soc

Commits: 1